Reading of data into arithmetic circuit and of result into memory



March 22, 1966 L. R. HARPER Original Filed May 27, 1958 17 Sheets-Sheetl COLUMN READ PUNCH EMITTER STATION STATION 10 2 3 CONTROL ROW OUTPUTPANEL ENCODER DECODER INPUT/OUTPUT COUNTER MATRIX 6 WORD SELECTEDDECIMAL ORDER DECIMAL TO BINARY ENCODER ARITHMETIC UNIT 1 MAGNETIC COREMEMORY A TIMING PULSE GENERATOR SCANNING PULSE INVENTOR RAT R O LEONARDR. HARPER ATTORNEY L. R. HARPER READING OF DATA INTO ARITHMETIC CIRCUITMarch 22, 1966 AND OF RESULT INTO MEMORY Original Filed May 27, 1958 17Sheets-Sheet 2 FIG. 2

CANCEL Q I T i l T TTI TT i li l I TI L T T+ 1 l LL T TT 1 4 4 TT TIL REVEN WODD March 22, 1966 HARPER 4 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 2'7, 1958 17 Sheets-Sheet 5 I F|s.3 WWWIL CM n," n'an n n'nn nn H c cnnnnnnn r Wwr f March 22, 1966 L. R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 1'7 Sheets-Sheet 4 FIG. 4

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March 22, 1966 L. R. HARPER 3,242,325

- REA F DATA 0 ARITHMETIC CIRCUIT D OF M 0 RES INTO EM RY Original FiledMay 27, 17 Sheets-Sheet 5 FIGJ S JLULUL FIG.6

March 22, 1966 L. R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 l7 Sheets-Sheet 6 FIG. 6a

March 2,2, 1966 L. R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 1'? Sheets-Sheet 7 FIG. 6b

March 22, 1966 Original Filed May 27, 1958 L. RQHARPER READING OF DATAINTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORY 17 Sheets-Sheet 8 FIG.6c

March 22, 1966 L. R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 9 FIG. 6 d

March 22, 1966 L. R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 10 FIG. 6e 0 March 22, 1966HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet l1 March 22, 1966 HARPER3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 12 1o M0 10 3 122 5 I:

SIZ H mg R2B M -.4 Q 435 M35 II F R15 Jl-8 JH 11-0 .n-i RA3/A March 22,1966 R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 15 SUB ' FIG. 6h

R/Iarch 22, 1966 HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 1L March 22, 1966 1.. R.HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet l5 FIG.6]

March 22, 1966 R. HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 17 Sheets-Sheet 16 FIGMO March 22, 1966 R.HARPER 3,242,325

READING OF DATA INTO ARITHMETIC CIRCUIT AND OF RESULT INTO MEMORYOriginal Filed May 27, 1958 A 17 Sheets-Sheet 17 FIG. 12a

FIG.140

United States Patent 3,242,325 READING OF DATA INTO ARITHIVIETIC CIRCUITAND OF RESULT INTO MEMORY Leonard R. Harper, San Jose, Calif., assignorto International Business Machines Corporation, New York, N.Y., acorporation of New York Original application May 27, 1958, Ser. No.738,199, now Patent No. 3,132,245, dated May 5, 1964. Divided and thisapplication Dec. 28, 1962, Ser. No. 247,970

3 Claims. (Cl. 235-176) This application is a division of United Statesapplication, Serial No. 738,199, filed May 27, 1958, now Patent No.3,132,245, issued May 5, 1964, by the inventor hereof, and assigned tothe assignee hereof. The subject matter of this application is alsodisclosed in United States application, Serial No. 42,114, filed July11, 1960, by the inventor hereof and assigned to the assignee hereof.

This invention relates to the electronic circuits of a binary computer.It more particularly concerns circuits for performing addition andsubtraction with two numbers recorded in a binary storage device.

An object of the invention is to provide an improved arithmetic circuitfor receiving alternately and serially, the binary informationconcerning two numbers and serially delivering back into availablememory structure the binary information relating to the result of theoperation effected on the two numbers.

Briefly stated, the present invention facilitates serial operation in abinary machine by using the word memory as it becomes available in theserial machine. Thus, two binary bits of information are readalternately and serially from memory into arithmetic circuitry, whichproduces a binary result. The result produced is then written into amemory bit location which was cleared incident to the arithmeticoperation. Addition of other digits is continued immediately under thecontrol of continuing timing pulses.

Other objects of the invention will be pointed out in the followingdescription and claims and illustrated in the accompanying drawings,which disclose, by way of example, the principle of the invention andthe best mode, which has been contemplated, of applying that principle.

In the drawings:

FIG. 1 is a block diagram of the data transfer device employing thepresent invention.

FIG. 2 illustrates the magnetic core storage and the decimal to binaryencoder of the data transfer device.

FIG. 3 is a timing diagram showing the signals appearing at variouspoints of the system.

FIGS. 4 and 5a to 5h give an explanation of the scanning system of thestorage and decimal to binary encoder.

FIGS. 6a to 6 assembled together as shown by FIG. 6, represents thegeneral diagram of the data transfer device and the arithmetic circuits.

FIGS. 7, 7a, 8, 8a, 9, 9a, 10, 10a, 11, 11a, 12, 12a, 13, 13a, 13b, 14,14a, 15 and 15a represent the elementary circuits used in the device andtheir conventional representation in the general block diagram.

FIG. 16 is a timing diagram showing various signals of a counter of thedevice.

GENERAL DESCRIPTION OF DATA TRANSFER DEVICE To aid in understanding thearithmetic circuits provided in accordance with the present invention, ageneral description of the data transfer device described and claimed inapplication Serial No. 738,199, mentioned above, will first be given.This data transfer device is one example of a data handling system withwhich the arithmetic circuits may be employed.

"ice

The data transfer device shown in FIG. 1 is operable to transfer data,which was read in decimal form by the read brushes at the read station 2of a card reader, into magnetic core storage 1 where it is stored inbinary form. The data transfer device is also operable to transfer data,which was read from the magnetic core storage 1 in binary form, to thepunch station 31of a card punch where it is recorded in decimal form.

These Operations are performed under control of the input/output matrix4, magnetic core decimal tobinary encoder 5, counter 6 and thearithmetic unit 7, which is the subject of the present invention.Encoder 5 contains the binary equivalent of the various decimal orders.When in a column of a card the digit n is read from a particular row,the pulse received on the read brush corresponding to that particularrow positions binary counter 6 through row encoder 8.

Under the control of counter 6, arithmetic unit 7 adds n times in thestorage the binary equivalent of the decimal order corresponding todigit n. Thus, for example, if the decimal digit 7 were sensed in thecolumn corresponding to the hundreds order, then, the binary equivalentof 10 namely, 1100100 would be added into storage 7 times resulting inthe value, 1010111100, which is the binary equivalent of the decimalnumber 700; The identification of the order associated with orrepresented by number n is performed through input/ output matrix 4- andthe column emitter 10, through control panel 9. The column emitter 10supplies pulses, available on the control panel at a rate of one percolumn of the card, to the input/output matrix 4 which is arranged insuch a way that the matrix supplies on one output group, pulsescorresponding to the various decimal orders, i.e. 10 10 '10", and on theother output group, pulses corresponding to the words, i.e. W1, W2 W16.Each order pulse conditions the switch of the corresponding magneticcore line of the encoder 5 while each word pulse conditions the switchof the magnetic core storage location in which the word is to be writtenor from which the word is to be read in order to allow the addition orthe subtraction in the conditioned word, of the number contained inconditioned line of the encoder 5.

The readout operation is performed in a manner whereby the machinesubtracts successively, from the word written in a location storage, thebinary equivalent of the 10 powers in decreasing order. Binary counter 6records the numer of subtractions that it was possible to perform. Theindication of counter 6 at the end of the operation is changed into adecimal by relay decoder 11 which ensures the picking up of punchelectromagnets at the punch station 3.

During this readout operation, the input/output matrix 4 and the columnemitter 10 perform the same duty as during the recording operation.Thus, the pulses corresponding to the columns into which the word is tobe punched are sent, through the control panel 9, to the input/outputmatrix 4. The pulses received on the word outputs condition the lineswitch of the storage location which contains the word to be punchedwhile the order pulses condition the line switches of the encoder 5, inwhich the equivalents of these orders are written in binary, in order toallow the sub-traction of the content of the encoder line from thestorage word.

Scanning pulse generator 13 is a common generator for both the storage 1and the encoder 5 while the timing pulse generator 42 provides thepulses which are necessary at the various times illustrated in FIG. 3.

Decimal binary encoding Referring to FIG. 2, storage 1 consists of amagnetic core matrix in which the recording is performed through thecoincidence of column and row half-currents. In the machine, a wordstored in storage 1 will be referred to as Word Y, while a word storedin the encoder will be referred to as word X. In a writing operationword X, which is in the encoder 5 serves as the addend while word Ywhich is addressed by the input/ output matrix 4 serves as the augend,the sum word being written into the storage position in which word Y isstored.

The timing of the operations of the machine is such that a bit of word Xis read, stored in the arithmetic unit 7 and regenerated, after which,the corresponding bit of word Y is read and added to the bit of word Xin the arithmetic unit 7, the resultant bit being written back into bitposition Y. To this end, the machine timing system supplies the pulsesshown in FIG. 3. A multivibrator (not shown) supplies the base signalsindicated by MV and starting from these signals, the timing circuits inthe timing pulse generator 42 supply pulses CPB, CPC, CPD, A, B, X, Y,C, D, T1, T2, etc.

The time interval during which oscillation A is at a high level is atime during which a bit of Word X'or word Yis read out of encoder 5 orstorage 1,.respectively, and applied to the arithmetic unit 7; it willbe referred to as read time or time A. Also, the time interval duringwhich oscillation B is at a high level is the time during which a bit ofinformation is regenerated in a word X position of the encoder 5 or abitof information from the arithmetic unit 7 is written in a word Yposition of storage 1. Identification is the same for times X and Yduring which bits of information, respectively, concerning words X andY, are read and written, that is, time A is the time when a bit ofinformation is read from -a word X or word Y position and time B is thetime when a bit of information is written into a corresponding word X orword Y position, respectively. Times C and D correspond to the readingand the writing of the cores of the successive columns of the matrix andencoder. Designations 1D, 3D, 5D 31D will be given'to the successivetimes during which the level of pulses D is high, and iD, 2D, 4D 30D tothe successive times during which the level of pulses C is high. Thetiming generator also supplies pulses existing only during one of thetimes or even during a portion of one of these times during which pulseX or Y is at a'high level.

In addition to these pulses, a chain of triggers forming a ring counter,of the type defined in the Proceedings of the IRE, volume 44, No. 9,September 1956, page 1169, in the timing pulse generator 42 suppliesunder the control of the main multivibrator, 16 pulses T1, T2 .T16, onlyT1 and T2 of which are shown on the diagram. To these basic pulses andtimes, have been added in g1, g2, g3, g4 the combinations which havebeen made with them for operating the matrix 1 and the encoder 5 whichare now to be considered.

7 Referring now to FIG. 2, the storage 1 consists of a 16-row and32-column magnetic core matrix in which information is recorded at arate of one word per row, while the encoder 5 consists of 32 columns,corresponding to those of the storage 1, and rows having magnetic coreslocated at predetermined positions. Nine of the ten rows of the encoder5 correspond to successive powers of 10 while 30 of the 32 columnscorrespond to successive powers of 2. The 10th row of the encoder 5 andthe 32nd column of both the storage 1 and encoder 5 consist of a cancelline having cores placed thereon corresponding to each row of thestorage 1 and predetermined rows and columns of the encoder 5. The coresare arranged in the encoder 5 in such a way that it is possible to readout on the columns the binary equivalent of the ,10 powers read inon therows. Thus, in row 10 there are cores in the 2nd, 5th and 6th columns(1O =2 +2 -|-2 =11OO1O0). The encoder 5 cores permanently contain 1 bitrepresentation. Each core of storage 1, except those on thecancel'c'olumn, is threaded by a column read wire, a column Write wire,a row read wire, a row write wire and a. sense wire while t cores on thecancel wire are threaded by the sense Wire and the row wire and areprovided to minimize the effects of half select current pulses inducedon the sense wire S. The sense wire S is wound through the matrix incheckerboard fashion to also minimize noise (due to half select currentpulses) induced on the sense wire S. Thus, due to the addition of thecancel core in each row of the storage 1, the sense wire S passesthrough 16 of the cores in each row in one sense and the remaining 16cores in the opposite sense. Hence, when a half select current pulse isapplied to a selected row and column of the storage 1, one of the coreson the selected row is selected or switched while the remaining 31 coresare half selected. The magnetic effect due to half selection of 16 ofthe cores is virtually cancelled by the opposite magnetic effect due tothe half selection of the remaining 15 cores ,of the selected row.

It will be noted that a column drive line, as for example, line 250,goes up through 16 cores of the storage land a predetermined number in.the encoder '5 and then down through a predetermined number in encoder5 and 16 cores of the storage 1. A core is provided'on the cancel row sothat the drive line will pass through an even number of cores and thesense wire S is wound through the cores of the encoder 5 in such amanneras to minimize the noise induced on the sense wire S due to the halfselection current pulse on a columndrive line. Similarly cores areprovided at predetermined points on the vertical cancel lines in theencoder 5 and'due to the direction in which the sense wire passesthroughthe cores of a row of the encoder 5 noiseinduced in the sensewire S due to the half selection current pulse on a row drive line isminimized.

In order to enter into storage .1, assuming it to be cleared, in binarya number read in decimal, as for example, the number 300, the switch ofline 10 of the encoder 5 is first closed and, through the scanningcircuits 1-3, the first bit position of line 10 is scanned and its valueis stored in the arithmetic unit 7. Then, the switch of a selected linein storage 1 is closed and the corresponding bit position of theselected line is scanned and its value (0) is added to the 'bit from thecorresponding position of the line 10 in the encoder 5 in the arithmeticunit 7 and the resultant bit is stored in the same bit position of theselected line.

Through scanning circuits 13 of storage 1 and encoder 5, and through thearithmetic unit 7, the corresponding bits are added, column aftercolumn, starting with the lowest power of 2, so that at the end of themachine'cycle, the content of line 10 of the encoder 5 is stored in theselected line of the storage 1. Since in row 10 of the encoder 5, thereare cores only in columns 2 2 and 2 the storage, at the end of theoperation, actually contains the binary equivalent of 100. Throughperforming this operation three times, the binary equivalent of 300 willhave been written. In order to read out a word from the storage, theprocess is similar, the arithmetic unit instructing to subtract, binaryelement after binary element, the content of a line of the decoder of astorage word.

Storage scanning FIGS. 4 and 5a5h show how the scanning system ofstorage 1 and encoder 5 operates. FIGS. 4 and Sa-Sh show only fourmagnetic cores for purposes of explanation, two of which (cores A and C)may belong to the Word addressed on time X, or word X, and the other-two(cores B and D) belong to word Y. In actuality the wires proceeding frompulse generators G3and G4 twice cross, not two rows of cores, but the.16 rows of the storage and the 9 rows of the encoder 5, each wire goingone way through a given column, and through the following or thepreceding column in the other way. The generators are operative onlywhen the corresponding switches are closed. In the present case,switches S4 and S5 are closed 011 times X, switches S4 and S5 on timesY,

switches S1 and S2 on one of the times T1, T2, etc., or T16 (see timetable). It should be noted that if cores A and C belong to a line ofencoder 5 and cores B and D to a line of the storage 1, switches S4 andS5 are closed by the order pulses and switches S4 and S5 by the wordpulses of the input/output matrix 4. It will be assumed that thecurrents travel from the pulse generators to ground.

FIG. 3 shows the current pulses g1, g2, g3 and g4, respectively,supplied by pulse generators G1, G2, G3, G4, and in FIGS. 50: to 5/1 thestate of the magnetization currents of cores A, B, C, D of FIG. 4 duringthe 8 successive periods of the basic multivibrator in which switches S1and S2 will be closed, i.e. during the time T1 of the primary chain ifthe first two columns of the matrix and encoder are concerned. Thediagrams and figures show that the binary information is successivelyread and written in cores A, B, C, D. Thus, referring to FIGS. 3, 4 and5a, during read time (A time) of word X, switches S1, S2, S4 and S5 areclosed and half select current pulses are applied from generators G1 andG3. Core A is switched since the half select current pulses pass in thesame direction through the core. No effect is sensed in core C since thehalf select current pulses from generators G1 and G3 pass in theopposite sense through the core C. Cores B and D are half selected dueto the half select current pulse from generator G3. However, they arehalf selected in opposite senses so that no noise would appear on thesense wire.

Now, referring to FIG. 5b, during Write time (B time) of word X,switches S1, S2, S4 and S5 remain closed and half select current pulsesare applied from generators G2 and G4. Core A is switched since. thehalf select current pulses pass in the same direction (opposite to thatduring read time) through the core. Again, no effect is sensed in core Csince the half select current pulses from generators G2 and G4 pass inopposite sense through core C. Also, again, cores B and D are halfselected due to the half select current pulse from generator G4.

Now, referring to FIG. 50, during read time (A time) of word Y, switchesS1 and S2 remain closed, S4 and S5 are opened and S4 and S5 are closedand half select current pulses are applied from generators G1 and G3.Core B is switched since the half select current pulses pass in the samedirection through the core. No effect is sensed in core D since the halfselect current pulses from generators G1 and G3 pass in opposite sensethrough the core D. Cores A and C are half selected due to the halfselect current pulse from generator G3. However, they are half selectedin the opposite sense so that no noise would appear on the sense wire.

Now, referring to FIG. 5d, during write time (B time) of word Y,switches S1, S2, S4 and S5 remain closed and half select current pulsesare applied from generators G2 and G4 only if it is desired to write a 1bit in this core. Core B is switched since the half select currentpulses pass in the same direction (opposite to that during read time)through the core. Again, no effect is sensed in core D since the halfselect current pulses from generators G2 and G4 pass in opposite sensethrough core D. Also, again, cores A and C are half selected due to thehalf select current pulse from generator G4.

Now, referring to FIG. 52, during read time (A time) of word X, switchesS1 and S2 remain closed, S4 and S5 are opened and S4 and S5 are closedand half select current pulses are applied from generators G1 and G4.Hence, in a manner similar to that previously described, only core C isswitched. Following this, half select current pulses are applied fromgenerators G2 and G3 to switch core C back to its original state asshown in FIG. 5 Similarly, core D is switched from one state to theother and then back as shown in FIGS. 5g and 511.

It should be noted that generator G1 always operates as a read driverwhile generator G2 always operates as a write driver. Also, generatorsG3 and G4 alternate as a read and write driver. Thus, generator G3operates as a read driver for odd columns and as a write driver for evencolumns whereas generator G4 operates as a write driver for odd columnsand as a read driver for even columns. Such an arrangement avoids therequirement of a current pulse generator for each column.

These operations are repeated according to the same sequence for othercolumns of the matrix during times T2 T16, thus allowing the scanning ofthe 32 columns of the matrix and encoder.

Input/ output matrix Refer first to FIG. 6g which shows the input/output matrix 4. It comprises 160 input hubs appearing in the controlpanel distributed among 16 rows of 10 columns, and 26 output terminals;16 correspond to the rows, 10 correspond to the columns. The figureshows only the hubs common to row lines W1, W15, W16 and to column linesi, 10, 10 10 Each hub of the matrix is connected to a voltage supply 120through two parallel channels each comprising resistors R1, R2, R3.Thus, for example, hub 11-8 is connected via a channel comprising RlA,R2A and R3A and via a parallel channel RIB, R2B and R3B to the voltagesupply 120. Connected to the junction spots of resistors R2A and R3A ofa channel are the output terminals of rows W1, W2 W16 and to thejunction spots of the corresponding resistors R2B and R3B of the otherchannel, the column output terminals 10 10' 10, i.

The junctions of resistors R1 and R2 are diode coupled to a negativevoltage supply 122 while the other end of resistors R3 is connected to anegative voltage supply 120 which is more negative than that of supply122. Consequently, since the anode of the diodes is connected to voltagesupply 122 and the cathode of the diodes is coupled via resistors R2 andR3 to the more negative voltage supply 120, current will flow fromvoltage supply 120 via resistors R3, R2 and the respective diodes tovoltage supply 122. Hence the output terminals of the matrix connectedto the junctions of resistors R2 and R3 will be at a relatively negativepotential to decondition the switching circuits associated with thestorage 1 and encoder 5.

Now, assume that a relatively positive potential is applied to the hub-7. Under this condition, the cathode of the diodes associated with thecolumn and the row which includes this hub is placed at a more positivepotential than their anode and these diodes will be cut off.Consequently, current will flow from voltage supply through resistorsR3B, R2B and RIB in the associated column, to the hub 115-7 and, inparallel, from voltage supply 120 through resistors R3A, RZA and R1A inthe associated row, to the hub 115-7. Hence, the potential at the outputterminals W15 and 10 will be raised to a relatively positive value tooperate the switching circuits associated with word 15 in storage 1 andorder 10" in encoder 5. There are fifteen other paths, corresponding tothe rows of the matrix, leading to the selected hub and nine otherpaths, corresponding to the columns of the matrix leading to theselected hub. The current fiowing in these paths are relatively smalland are such that the associated diodes are not cut oif with theresulting effect being that the corresponding output terminals aremaintained at relatively negative potentials.

In order to understood how the input/ output matrix 4 performs itsselection function, assume that a 6 digit number located in columns 11to 16 of the punched card is to be entered in (or read out of) thestorage 1. Consequently, with the 6 hubs J11 I16 of the control panel 9,successive pulses are available, supplied by column emitter 121, whencolumns 11 to 16 of the punched card pass under the read brushes.

Assuming that in the card, the unit digit is punched in column 16, thetens digit in column 15, etc., and that it is desired to record thepunched word in word position

1. ARITHMETIC APPARATUS FOR COMBINING A BINARY CODED WORD X TO A BINARYCODED WORD Y COMPRISING A MEMORY DEVICE FOR STORING THE WORDS X AND Y,AT LEAST THE MEMORY FOR STORING ONE OF SAID WORDS BEING OF A TYPE INWHICH A DIGIT STORE IN ONE CONDITION IS SWITCHED AND THEREBY ALWAYSEFFECTIVELY CLEARED OF DATA WHEN A BINARY DIGIT IS READ FROM SAID MEMORYDEVICE, TIMING MEANS FOR REPRODUCING DIGITS OF THE WORDS SERIALLY INASCENDING ORDERS AND ALTERNATELY AS TO THE WORDS, LOGIC MEANSOPERATIVELY ASSOCIATED WITH A BISTABLE CIRCUIT FOR RECEIVING THE DIGITSOF BOTH WORDS FOR SELECTIVELY CHANGING THE BISTABLE CIRCUIT TO GENERATESUCCESSIVE DIGITS OF AN ARITHMETIC RESULT, AND MEANS FOR RECORDING ABINARY SIGNAL CORRESPONDING TO THE STATUS OF SAID BISTABLE CIRCUIT INTOSAID DIGIT STORE OF SAID MEMORY DEVICE EFFECTIVELY CLEARED OF DATA WHENA DIGIT IS READ FROM SAID MEMORY TO CREATE SAID ARITHMETIC RESULT.